The performance of semiconductor device fabrication operations such as plasma-assisted etch processes is often essential to the success of a semiconductor device processing workflow. However, optimization or tuning of the etch processes and/or the tools associated with them (e.g., etch reactors, lithography masks, etc.) may prove technically difficult and time-consuming, often involving skilled personnel manually adjusting etch process parameters or tool component designs to generate the desired target feature profile. Currently, no automated procedure, of sufficient accuracy, exists which may be relied upon to determine the values of process parameters responsible for a desired etch profile.
Certain models simulate the physical and/or chemical processes occurring on semiconductor substrate surfaces during etch processes. Examples of such models include etch profile models (EPMs) implemented as behavioral models (e.g., the SEMulator3D available from Coventor (a Lam Research Company) of Cary, N.C.) or implemented as models of surface reactions; see e.g., models of M. Kushner and co-workers as well as the those of Cooperberg and co-workers. The former are described in Y. Zhang, “Low Temperature Plasma Etching Control through Ion Energy Angular Distribution and 3-Dimensional Profile Simulation,” Chapter 3, dissertation, University of Michigan (2015), and the latter in Cooperberg, Vahedi, and Gottscho, “Semiempirical profile simulation of aluminum etching in a Cl2/BCl3 plasma,” J. Vac. Sci. Technol. A 20(5), 1536 (2002), both of which are hereby incorporated by reference in their entireties. Additional description of the etch profile models of M. Kushner and co-workers may be found in J. Vac. Sci. Technol. A 15(4), 1913 (1997), J. Vac. Sci. Technol. B 16(4), 2102 (1998), J. Vac. Sci. Technol. A 16(6), 3274 (1998), J. Vac. Sci. Technol. A 19(2), 524 (2001), J. Vac. Sci. Technol. A 22(4), 1242 (2004), J. Appl. Phys. 97, 023307 (2005), each of which is also hereby incorporated by reference in its entirety. Additional description of etch profile models of Coventor can be found in U.S. Pat. No. 9,015,016 filed Nov. 25, 2008 by Lorenz et al., and U.S. Pat. No. 9,659,126 filed Jan. 26, 2015 by Greiner et al., each of which is also hereby incorporated by reference in its entirety. Such disclosed models may benefit from further development to approach the degree of accuracy and reliability desired by the semiconductor processing industry.
Background and contextual descriptions contained herein are provided solely for the purpose of generally presenting the context of the disclosure. Much of this disclosure presents work of the inventors, and simply because such work is described in the background section or presented as context elsewhere herein does not mean that it is admitted to be prior art.